Technical Field
This invention relates generally to the field of semiconductors, and more particularly, to forming a zero threshold voltage fin field effect transistor (FinFET) device.
Related Art
A typical integrated circuit (IC) chip includes a stack of several levels or sequentially formed layers of shapes. Each layer is stacked or overlaid on a prior layer and patterned to form the shapes that define devices (e.g., field effect transistors (FETs)) and connect the devices into circuits. In a typical state of the art complementary insulated gate FET process, such as what is normally referred to as CMOS, layers are formed on a wafer to form the devices on a surface of the wafer. Further, the surface may be the surface of a silicon layer on a silicon on insulator (SOI) wafer. A simple FET is formed by the intersection of two shapes, a gate layer rectangle on a silicon island formed from the silicon surface layer. Each of these layers of shapes, also known as mask levels or layers, may be created or printed optically through well-known photolithographic masking, developing, and level definition (e.g., etching, implanting, deposition, etc.).
The FinFET is a transistor design that attempts to overcome the issues of short-channel effect encountered by deep submicron transistors, such as drain-induced barrier lowering (DIBL). Such effects make it harder for the voltage on a gate electrode to deplete the channel underneath and stop the flow of carriers through the channel—in other words, to turn the transistor off. By raising the channel above the surface of the wafer instead of creating the channel just below the surface, it is possible to wrap the gate around all but one of its sides, providing much greater electrostatic control over the carriers within it.
FET transistor devices, whether planar, fin, or otherwise, each have certain measurements that can be used to measure performance against other devices. One such measurement is that of threshold voltage (Vt). Threshold voltage can be defined as the value of the gate-source voltage when the conducting channel just begins to connect the source and drain contacts of the transistor, allowing significant current. In ICs, core MOSFET's having higher Vt (0.3V range) in combination with the scaled drain voltage (Vdd) can create a limited dynamic range for analog input signals. With the technology node progression, the input signal range can get smaller, but the noise signal's magnitude usually remains the same. This can result in poor signal-to-noise ratio and smaller operational bandwidth.
In contrast, a zero Vt (ZVt) MOSFET (or natural transistor) generally turns on at or near gate voltage (Vg)=0V. These zero Vt MOSFETs are commonly used in low voltage OP Amps, analog and/or digital and/or mixed signal circuitries, low power and/or interface circuit applications. An application of zero Vt MOSFET in the circuits can significantly expand useful operating range of the signal, thus enabling rail-to-rail circuit operation of very low voltage analog circuits. ZVt MOSFETs are commonly used as pass gates, mainly due to the low gate MOS capacitance and higher Ft (operating frequency) at near zero gate voltage (Vg).
While FinFET technology can provide superior levels of scalability, new challenges can arise in designing and/or fabricating these devices. For example, processes used to adjust Vt during the fabrication process of a platform device may be unworkable or have unintended effects in the FinFET model.